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11	1 ****************************************************** * GAMESS VERSION = 6 MAY 1998 * Add to Reading List Source URL: www.msg.ameslab.gov Language: English - Date: 2013-11-12 12:31:45 Chemistry Nature Quantum chemistry Chemical bonding Theoretical chemistry Computational chemistry Atomic physics Atomic orbital Basis set Integral Molecular orbital CPU time
12	Accurate emulation of CPU performance Tomasz Buchert1 , Lucas Nussbaum2 , and Jens Gustedt1 1 2 INRIA Nancy – Grand Est Add to Reading List Source URL: www.loria.fr Language: English Computer architecture Computing Computer engineering Clock signal Central processing unit CPU time Multi-core processor Load SpeedStep Clock rate Opteron Benchmark
13	Accurate emulation of CPU performance Tomasz Buchert1 Lucas Nussbaum2 1 Add to Reading List Source URL: www.loria.fr Language: English - Date: 2011-10-12 09:35:39 Central processing unit Computing Engineering Computer performance Emulator Processor design CPU time
14	RT-OpenStack: CPU Resource Management for Real-Time Cloud Computing Sisu Xi, Chong Li, Chenyang Lu, Christopher D. Gill Meng Xu, Linh T.X. Phan, Insup Lee, Oleg Sokolsky Add to Reading List Source URL: www.cse.wustl.edu Language: English - Date: 2015-05-26 00:47:06
15	Warning: no access to tty (Bad file descriptor). Thus no job control in this shell. This is DQS job h2.mcscGAMESS execution scriptThis job is running on host pt.msg.chem.iastate.edu under operating sy Add to Reading List Source URL: www.msg.ameslab.gov Language: English - Date: 2015-10-05 14:57:05 H2 CPU time
16	CPU+GPU Load Balance Guided by Execution Time Prediction Jean-François Dollinger Vincent Loechner Add to Reading List Source URL: impact.gforge.inria.fr Language: English - Date: 2015-02-10 08:43:14
17	It’s Time for Low Latency Stephen M. Rumble, Diego Ongaro, Ryan Stutsman, Mendel Rosenblum, and John K. Ousterhout Stanford University Abstract CPU Speed Add to Reading List Source URL: www.scs.stanford.edu Language: English - Date: 2011-04-15 13:57:29
18	6 Mechanism: Limited Direct Execution In order to virtualize the CPU, the operating system needs to somehow share the physical CPU among many jobs running seemingly at the same time. The basic idea is simple: run one pro Add to Reading List Source URL: pages.cs.wisc.edu Language: English - Date: 2016-01-21 09:11:42
19	...................................................................................................................................... Ehcache v. 2.4 User Guide Add to Reading List Source URL: www.ehcache.org Language: English - Date: 2016-02-25 06:01:44 Cache Terracotta Inc. Web cache Ehcache CPU cache Time to live Caching SAN adapter Database caching
20	Automationdirect.com™ Direct Logic 205 Smart Distributed System CPU F2-SDS-1 Order Number: F2-SDS-1-M Add to Reading List Source URL: facts-eng.com Language: English - Date: 2013-08-15 08:22:35 Engineering Computing Automation Industrial automation SDS Protocol Central processing unit Computer hardware Time-sharing Xerox Scientific Data Systems Samsung SDS